max7000系列设计必备(pdf 6页)

 High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX® architecture
 5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
 Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
 Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
 5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
 PCI-compliant devices available
f For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.

Open-drain output option in MAX 7000S devices

Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls

Programmable power-saving mode for a reduction of over 50
%
in
each macrocell

Configurable expander product-term distribution, allowing up to
32 product terms per macrocell

44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

Programmable security bit for protection of proprietary designs

3.3-V or 5.0-V operation
– MultiVolt
TM
I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices……
..............................

上一篇：GC-CAM中修补铜箔针孔的方法(pdf 4页)

下一篇：NIOS参与cyc版原理图(pdf 9页)

嘉华PLC编程手册(doc 45页)

quartus II中文用户教程(pdf 50页)

端子或连接器件用（端 接和／或分接）接线盒的特殊要求(pdf 27

ALTERA 新一代CPLD简介

PID控制模块培训资料(pdf 40页)

印刷电线板原始制造商资质认证手册(英文版)(doc 51页)